SAN JOSE, Calif.--(BUSINESS WIRE)--PLDA, the industry leader in PCI Express® interface IP solutions, today unveiled innovative PCIe PHY and PCIe Controller interop strategies that are ideally suited to ASIC and SoC designers developing PCIe-based designs. These strategies, which combine PLDA’s strong partner ecosystem, and a stringent 4-step controller and PHY collaborative validation process, will be presented at IP-SoC China on September 14, 2017.
Integration between a PCIe controller and PHY has become increasingly complex as PCIe speeds rise, and PIPE specifications accounting for different modes and features become even more intricate, requiring more robust verification and validation strategies. In conjunction with its PLDA Ecosystem partners, PLDA's stringent 4-step integration and validation solution spans the entire process from simulation verification all the way to silicon tape-out, including:
- Functional verification of the controller with multiple 3rd-party VIPs
- PHY interoperability verification using PLDA’s unique PHY Test suite
- PHY test chip hardware validation
- Tape-outs and PCI-SIG Compliance
PLDA’s end-to-end process draws on over twenty years of experience in integrating custom PHYs, either by incorporating a customer's PIPE compliant PHY or by helping designers integrate non-PIPE PHYs. PLDA’s integrated Ecosystem solutions include verification frameworks for key VIP providers and PLDA’s easy-to-use PHY interop test suite, providing a comprehensive set of test cases for every aspect of PHY operation. This comprehensive approach has delivered more than 360 tested and verified tape-outs for PCIe products, spanning PCIe speeds from PCIe 1.0 to PCIe 4.0, with multiple PHY vendors on various process nodes.
According to Arnaud Schleich, CEO of PLDA, “PLDA’s strategy delivers an unmatched flexibility, providing customers with the ability to choose their integrated solution based on multiple factors, including design performance, specific foundry and node considerations, price or licensing considerations, and specific PHY features for each design.” Schleich added “This flexibility has been a key component in PLDA’s successful tape-out of over 360 ASICs that included a broad array of different PHYs on many different process nodes and foundries.”
For more information:
- See PLDA’s presentation at IP-SoC China on September 14, 2017 in Shanghai, China. To register for the event, visit the IP-SoC website at http://www.design-reuse-embedded.com/ipsocdays/shanghai2017.jsp.
- Visit the PLDA Ecosystem webpage on the PLDA website at https://www.plda.com/partners/phy-partners for more information on the extensive PLDA Ecosystem of partners.
About PLDA
PLDA has been successfully delivering PCI and PCI
Express IP for more than 20 years. With over 6,200 licenses, PLDA has
established a vast customer base and the world’s broadest PCIe
ecosystem. PLDA has maintained its leadership over four generations of
PCI Express specifications, enabling customers to reduce risk and
accelerate time to market for their ASIC and FPGA based designs. PLDA
provides a complete PCIe solution with its IP cores, FPGA boards for
ASIC prototyping, PCIe BFM/testbench, PCIe drivers and APIs. PLDA is a
global company with offices in North America (San Jose, California) and
Europe (France, Italy, Bulgaria).
