SANTA CLARA, Calif.--(BUSINESS WIRE)--Memoir Systems Inc., the Semiconductor Intellectual Property (SIP) provider that delivers breakthrough memory performance, today announced that the company’s co-founder and CTO, Dr. Sundar Iyer will be presenting at DesignCon 2012 on Wednesday, February 1, 2012, beginning at 11:05am. Dr. Iyer’s presentation, “Algorithmic Memory: An Order of Magnitude Performance Increase for Next Generation SoC” will introduce a new and unique solution to the memory performance bottlenecks that plague many of today’s SoC-based application designs.
Historically, circuits and advances in lithography have been used at every generation as the approach to enhance memory performance. Unfortunately, these approaches alone do not give enough performance improvement and are not keeping up with applications that require higher memory performance. Therefore memory performance remains a bottleneck with traditional approaches, leading to the often quoted ‘processor memory’ gap. Dr. Iyer will present a completely new technique – algorithmic memory, which uses the power of algorithms to make existing embedded memory up to ten times faster. In particular, algorithms, which are implemented in standard RTL logic, and are built around existing embedded memory to expose multiple memory interfaces. These interfaces individually provide true random access memory operations, and can be used independently and in parallel to increase the total number of memory operations per second (MOPS).
Dr. Iyer’s expertise spans the areas of network and memory algorithms, system architecture, and component design. As part of his PhD thesis, he developed a mathematical framework for high-performance networking. As a founding member and senior architect at SwitchOn Networks (acquired by PMC-Sierra in ‘00), he developed algorithms for associative memory and deep packet classification. In 2008, Iyer was awarded the MIT technology review (TR35) young innovator award for his work on network memory.
WHAT: DesignCon 2012 Technical Session 7-WA4 — “Algorithmic Memory: An Order of Magnitude Performance Increase for Next Generation SoCs"
WHO: Sundar Iyer, co-founder and CTO, Memoir Systems
WHEN: Wednesday, February 1, 2012 at 11:05 a.m. to 11:45 a.m.
WHERE: Great America 3 (room), Santa Clara Convention Center, Santa Clara, CA
Further information on the event can be found at http://www.designcon.com/. For more details on Memoir’s Algorithmic Memory technology, go to: www.memoir-systems.com/.
About Memoir Systems, Inc.
Memoir Systems, Inc. is a provider of breakthrough embedded memory technology that is delivered as Semiconductor Intellectual Property (SIP). The company utilizes its patent-pending Algorithmic Memory™ technology to increase the performance of existing memory macros – up to 10X more Memory Operations Per Second (MOPS). In addition, the technology significantly shortens memory development time, and may lower area and power consumption if performance is kept the same. Memoir’s technology is process, node, and foundry independent, and can be readily integrated into any existing SoC (ASICs, ASSPs, GPPs and FPGAs) design flow. The company’s strategy is to deliver technology and business benefits to its customers and partners by providing solutions that are drop-in replacements for existing embedded memory. Memoir Systems is based in Santa Clara, California, and has additional research and development facilities located in Hyderabad, India. For more information, visit www.memoir-systems.com.
Memoir, Algorithmic Memory, Synthesized Memory and the Memoir Systems logo are trademarks or registered trademarks of Memoir Systems Inc. in the United States and other countries. Memoir Systems and other parties may also have trademark rights in other terms used herein.
The URL for this release is located at: www.memoir-systems.com