SAN JOSE, Calif.--(BUSINESS WIRE)--Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, announced today the 5.1 release of its SpyGlass® and GenSys® platforms. The release contains significant usability improvement and enhancements to address complexity, size and performance challenges for the next wave of SoC designs. The release also offers unique new capabilities enabled by the integration of technologies from SpyGlass for static analysis, BugScope™ for dynamic verification and GenSys for design exploration.
A key focus of the release is to enhance the user experience. Several new enhancements are now available in Atrenta Console, the graphical user interface, including an intuitive layout with expanded space for debug, message grouping and filtering, and the ability to trace signal drivers across multiple hierarchies. SpyGlass reports now leverage the power of HTML navigation with a top level landing page that allows easy navigation to all the relevant reports for the project. These are also linked to the Atrenta DashBoard allowing complete traceability of results from project managers all the way to the engineer responsible for a design block. Several key enhancements are available in the SpyGlass Tcl shell for design read and setup, design and results query, and customized reporting.
The hierarchical SoC abstraction flow, now available for multiple SpyGlass technologies, is significantly enhanced for usability, especially in the handling of mismatches between block and SoC level assumptions. This unique flow provides an order of magnitude improvement in run time, memory footprint and noise when applied to large SoC designs and is the only way to scale for the next wave of billion gate designs.
To facilitate CDC signoff, SpyGlass CDC now generates SystemVerilog assertions (SVA) for constraints/assumptions and complex scenarios for further validation in the simulation environment. This hybrid verification flow leverages the power of dynamic verification in addition to existing structural and formal CDC verification. This hybrid verification flow will soon be further enriched with a new BugScope interface enabling CDC users to interactively query the BugScope dynamic database for CDC properties.
Physically-aware RTL power estimation is now supported by SpyGlass Power. Using SpyGlass Physical technology, this capability provides fast and accurate RTL power estimation with superior correlation. For designs targeting 28nm or lower process nodes, physical placement information is critical to accuracy of power estimation. Also available is an enhanced flow for gate-level power estimation using RTL simulation data.
With a focus on optimizing standby power in memories, SpyGlass Power now has the ability to generate new conditions for enabling light sleep mode, taking into account power saving tradeoffs. This includes insertion of new light sleep control logic in the RTL and sequential equivalence checking. SpyGlass Power Verify has new graphical debug features to visualize power intent via a hierarchical design explorer and schematics. The power intent browser also provides dynamic referencing to the UPF file.
SpyGlass TXV now provides better quality of results for multi-cycle path verification with improved enable detection and advanced formal algorithms. Random resistive faults, or deeply embedded and hard-to-detect faults, can result in long ATPG runtimes and loss of coverage. SpyGlass DFT DSM has been enhanced to identify such faults and display the results in a fault browser. Also added is support for transition fault coverage for launch on shift (LOS), in addition to the previously supported launch on capture (LOC) mode.
SpyGlass Physical has been enhanced to handle incomplete or immature data input, a common practice at the early stages of design exploration. The tool is now more tolerant of this “dirty input” which may have semantic inconsistencies in the RTL, .lib, LEF files or between these views.
Integration between the GenSys and SpyGlass platforms has been enhanced in this release with the ability to share project files between the two platforms, thus enabling a smoother work flow from RTL creation to analysis and verification. GenSys RTL has been enhanced with new capabilities for hierarchy manipulation, support for virtual hierarchies and feed throughs.
“As the market leading RTL platform provider, Atrenta continues to drive innovation in RTL analysis, verification and exploration. Our customers have come to rely on us for RTL signoff and for us, SpyGlass 5.1 is a major milestone in support of that mission," said Piyush Sancheti, vice president of product marketing at Atrenta. "I am quite encouraged by the positive feedback from our early customer partners. We expect our broader customer base to see significant productivity gains from adopting the release.”
About Atrenta
Atrenta’s SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.
SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com
© 2013 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, GenSys and SpyGlass are registered trademarks and BugScope is a trademark of Atrenta Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.
