ALBANY, N.Y.--(BUSINESS WIRE)--Through a series of lectures and workshops, SEMATECH will address R&D challenges and closing key infrastructure technology gaps from July 8–12 at SEMICON West in San Francisco, CA.
SEMATECH experts will discuss the challenges which are affecting progress in next-generation lithography techniques, new materials and processes for sub-20 nm manufacturing as well as present a variety of advances in new materials and device structures and lithography.
“In order to prepare for major industry transitions that will stress the industry’s resources over the next decade, we must evolve our infrastructure collaborations to address rapidly evolving technical and business model challenges,” said Dan Armbrust, president and CEO of SEMATECH. “SEMICON West is an important conference that brings together manufacturers, suppliers, developers, academia and research consortia to share knowledge and discuss how to meet these challenges in order to sustain growth into the future.”
On July 10, Armbrust will be participating in SEMI’s executive R&D panel, “A Conversation on the Future of Semiconductor Technology.” Collaborative research experts will address the technological and financial challenges in semiconductor design, process technology and manufacturing, and share how technical contributions and synergies from all sectors of the industry are required to achieve industry-wide goals.
SEMATECH experts who are scheduled to speak on the SEMICON West TechXPOT stage, in the North and South Halls of the Moscone Center include:
- Paul Kirsch, SEMATECH’s director of Front End Processes, “Non-Silicon R&D Challenges and Opportunities,” July 9 at 11:30 a.m., South Hall
- Stefan Wurm, SEMATECH’s director of Lithography, “EUV Lithography: Status and Outlook,” July 10 at 10:55 a.m., South Hall
- Abbas Rastegar, SEMATECH Fellow “Challenges of Nanodefectivity,” July 10 at 11:50 a.m., North Hall
- Mark Neisser, SEMATECH research manager, “ITRS Front End of Line Technologies: Lithography,” July 11 at 1 p.m., South Hall
Additionally, SEMATECH will host several public workshops at the San Francisco Marriott Marquis during SEMICON West:
- Participants will address the challenges associated with infrastructure gaps, particle metrology and filtration for the reduction and prevention of nanoparticles in solutions at the SEMATECH Workshop on Nanoparticle Defectivity Issues in Solutions on July 9 at 8 a.m.
- Equipment suppliers, semiconductor researchers and device manufacturers will discuss how they are applying new inspection and metrology technologies as well as modified or enhanced existing techniques to improve 3D interconnect processes at the SEMATECH Workshop on 3D Interconnect Metrology on July 10 at 8 a.m.
- Co-sponsored by SEMI and SEMATECH, the Enabling Supply Chain R&D through Collaboration Workshop will identify the most significant affordability challenges for semiconductor R&D and explore new collaborative opportunities that address these challenges on July 10 at 1:30 p.m.
- A half-day preview of this year’s International Technology Roadmap for Semiconductors will be offered at the Summer ITRS Public Conference on July 11.
Some of SEMATECH’s most prominent technologists in the nanoelectronics industry will be attending SEMICON West. To arrange for meeting attendance or interviews with executives and technical experts, please contact erica.mcgill@sematech.org.
About SEMATECH
For over 25 years, SEMATECH®, the international consortium of leading semiconductor device, equipment, and materials manufacturers, has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Through our unwavering commitment to foster collaboration across the nanoelectronics industry, we help our members and partners address critical industry transitions, drive technical consensus, pull research into the industry mainstream, improve manufacturing productivity, and reduce risk and time to market. Information about SEMATECH can be found at www.sematech.org. Twitter: www.twitter.com/sematech
