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June 25, 2024 10:45 AM Eastern Daylight Time

Cadence Expands System IP Portfolio with Network on Chip to Optimize Electronic System Connectivity

The Cadence Janus Network-on-Chip (NoC) efficiently manages simultaneous high-speed communications within and between silicon components with minimal latency. This enables customers to achieve their power, performance and area (PPA) targets faster and with lower risk, freeing up valuable engineering resources for SoC differentiation. (Graphic: Business Wire)
The Cadence Janus Network-on-Chip (NoC) efficiently manages simultaneous high-speed communications within and between silicon components with minimal latency. This enables customers to achieve their power, performance and area (PPA) targets faster and with lower risk, freeing up valuable engineering resources for SoC differentiation. (Graphic: Business Wire)
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